 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Semiconductor HI5812 CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold Description The HI5812 is a fast, low power, 12-bit, successive approximation analog-to-digital converter. It can operate from a single 3V to 6V supply and typically draws just 1.9mA when operating at 5V. The HI5812 features a built-in track and hold. The conversion time is as low as 15s with a 5V supply. The twelve data outputs feature full high speed CMOS threestate bus driver capability, and are latched and held through a full conversion cycle. The output is user selectable: (i.e.) 12bit, 8-bit (MSBs), and/or 4-bit (LSBs). A data ready flag, and conversion-start inputs complete the digital interface. An internal clock is provided and is available as an output. The clock may also be over-driven by an external source. August 1997 Features * Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 20s * Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .50 KSPS * Built-In Track and Hold * Guaranteed No Missing Codes Over Temperature * Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V * Maximum Power Consumption. . . . . . . . . . . . . . .25mW * Internal or External Clock Applications * Remote Low Power Data Acquisition Systems * Digital Audio * DSP Modems * General Purpose DSP Front End * P Controlled Measurement System * Professional Audio Positioner/Fader Ordering Information PART NUMBER HI5812JIP HI5812KIP HI5812JIB HI5812KIB HI5812JIJ HI5812KIJ INL (LSB) (MAX OVER TEMP.) 1.5 1.0 1.5 1.0 1.5 1.0 TEMP. RANGE (oC) PKG. NO. E24.3 E24.3 M24.3 M24.3 PACKAGE -40 to 85 24 Ld PDIP -40 to 85 24 Ld PDIP -40 to 85 24 Ld SOIC -40 to 85 24 Ld SOIC -40 to 85 24 Ld CERDIP F24.3 -40 to 85 24 Ld CERDIP F24.3 Pinout HI5812 (PDIP, CERDIP, SOIC) TOP VIEW DRDY (LSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 VDD 23 OEL 22 CLK 21 STRT 20 VREF 19 VREF+ 18 VIN 17 VAA+ 16 VAA15 OEM 14 D11 (MSB) 13 D10 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright (c) Harris Corporation 1997 File Number 3214.4 6-1789 HI5812 Functional Block Diagram STRT VDD VSS VIN CONTROL + TIMING 32C VREF+ OEM 16C D11 (MSB) 50 SUBSTRATE 8C D10 4C 2C VAA+ C VAA64C 63 32C D7 16C 8C 4C 2C C D3 C D2 D1 VREF D0 (LSB) OEL 12-BIT SUCCESSIVE APPROXIMATION REGISTER 12-BIT EDGE TRIGGERED "D" LATCHED D8 D9 CLOCK CLK DRDY TO INTERNAL LOGIC D6 D5 D4 P1 6-1790 HI5812 Absolute Maximum Ratings Supply Voltage VDD to VSS . . . . . . . . . . . . . . . . . . . . (VSS -0.5V) < VDD < +6.5V VAA+ to VAA-. . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V) VAA+ to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Analog and Reference Inputs VIN , VREF+, VREF-. . . . . . . . . (VSS -0.3V) < VINA < (VDD +0.3V) Digital I/O Pins . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD +0.3V) Thermal Information Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CERDIP Package . . . . . . . . . . . . . . . . 60 12 PDIP Package . . . . . . . . . . . . . . . . . . . 80 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 75 N/A Maximum Junction Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65C to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range PDIP, SOIC, and CERDIP Packages . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF - = GND, CLK = External 750kHz, Unless Otherwise Specified 25oC -40oC TO 85oC MAX MIN MAX UNITS PARAMETER ACCURACY Resolution Integral Linearity Error, INL (End Point) Differential Linearity Error, DNL J K J K Gain Error, FSE (Adjustable to Zero) Offset Error, VOS (Adjustable to Zero) Power Supply Rejection, PSRR Offset Error PSRR Gain Error PSRR DYNAMIC CHARACTERISTICS Signal to Noise Ratio, SINAD RMS Signal RMS Noise + Distortion Signal to Noise Ratio, SNR RMS Signal RMS Noise Total Harmonic Distortion, THD J K J K J K Spurious Free Dynamic Range, SFDR J K J K J K TEST CONDITIONS MIN TYP 12 VREF = 4V VDD = VAA+ = 5V 5% VDD = VAA+ = 5V 5% fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz fS =Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - 0.1 0.1 1.5 1.0 2.0 1.0 3.0 2.5 2.0 1.0 0.5 0.5 12 - 1.5 1.0 2.0 1.0 3.0 2.5 2.0 1.0 0.5 0.5 Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB 68.8 69.2 71.0 71.5 70.5 71.1 71.5 72.1 -73.9 -73.8 -80.3 -79.0 -75.4 -75.1 -80.9 -79.6 - - - dB dB dB dB dB dB dB dB dBc dBc dBc dBc dB dB dB dB 6-1791 HI5812 Electrical Specifications VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF - = GND, CLK = External 750kHz, Unless Otherwise Specified (Continued) 25oC PARAMETER ANALOG INPUT Input Current, Dynamic Input Current, Static Input Bandwidth -3dB Reference Input Current Input Series Resistance, RS Input Capacitance, CSAMPLE Input Capacitance, CHOLD DIGITAL INPUTS OEL, OEM, STRT High-Level Input Voltage, VIH Low-Level Input Voltage, VIL Input Leakage Current, IIL Input Capacitance, CIN DIGITAL OUTPUTS High-Level Output Voltage, VOH Low-Level Output Voltage, VOL Three-State Leakage, IOZ Output Capacitance, COUT CLOCK High-Level Output Voltage, VOH Low-Level Output Voltage, VOL Input Current TIMING Conversion Time (tCONV + tACQ) (Includes Acquisition Time) Clock Frequency Internal Clock, (CLK = Open) External CLK (Note 2) Clock Pulse Width, tLOW, tHIGH Aperture Delay, tDAPR Clock to Data Ready Delay, tD1DRDY Clock to Data Ready Delay, tD2DRDY Start Removal Time, tRSTRT Start Setup Time, tSUSTRT Start Pulse Width, tWSTRT Start to Data Ready Delay, tD3 DRDY Clock Delay from Start, tDSTRT Output Enable Delay, tEN Output Disabled Delay, tDIS POWER SUPPLY CHARACTERISTICS Supply Current, IDD + IAA NOTE: 2. Parameter guaranteed by design or characterization, not production tested. 1.9 5 8 mA External CLK (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) 20 200 0.05 100 75 85 10 300 2 35 105 100 30 60 4 65 60 20 80 400 1.5 50 150 160 105 30 95 20 150 0.05 100 75 100 15 500 1.5 70 180 195 120 50 120 s kHz MHz ns ns ns ns ns ns ns ns ns ns ns ISOURCE = -100A (Note 2) ISINK = 100A (Note 2) CLK Only, VIN = 0V, 5V 4 1 5 4 1 5 V V mA ISOURCE = -400A ISINK = 1.6mA Except DRDY, VOUT = 0V, 5V Except DRDY 4.6 20 0.4 10 4.6 0.4 10 V V A pF Except CLK, VIN = 0V, 5V 2.4 10 0.8 10 2.4 0.8 10 V V A pF In Series with Input CSAMPLE During Sample State During Hold State At VIN = VREF+, 0V Conversion Stopped 50 0.4 1 160 420 380 20 100 10 100 10 A A MHz A pF pF TEST CONDITIONS MIN TYP MAX -40oC TO 85oC MIN MAX UNITS 6-1792 HI5812 Timing Diagrams 1 CLK (EXTERNAL OR INTERNAL) tD1DRDY tLOW tHIGH STRT tD2DRDY DRDY 2 3 4 5 - 14 15 1 2 3 D0 - D11 DATA N - 1 DATA N VIN OEL = OEM = VSS HOLD N TRACK N TRACK N + 1 FIGURE 1. CONTINUOUS CONVERSION MODE 15 CLK (EXTERNAL) 1 2 2 2 3 4 5 tRSTRT tSUSTRT tWSTRT STRT tD3DRDY DRDY HOLD VIN TRACK HOLD FIGURE 2. SINGLE SHOT MODE EXTERNAL CLOCK 6-1793 HI5812 Timing Diagrams (Continued) 15 CLK (INTERNAL) 1 2 3 4 5 tRSTRT tDSTRT tWSTRT STRT DON'T CARE tD3DRDY DRDY HOLD TRACK HOLD VIN FIGURE 3. SINGLE SHOT MODE INTERNAL CLOCK OEL OR OEM tEN 90% 50% D0 - D3 OR D4 - D11 HIGH IMPEDANCE TO HIGH HIGH IMPEDANCE TO LOW TO OUTPUT PIN 50% 10% +2.1V 50pF tDIS 1.6mA -1.6mA FIGURE 4A. FIGURE 4. OUTPUT ENABLE/DISABLE TIMING DIAGRAM FIGURE 4B. 1.6mA +2.1V 50pF -400A FIGURE 5. GENERAL TIMING LOAD CIRCUIT 6-1794 HI5812 Typical Performance Curves 1.0 VDD = VAA+ = 5V, VREF+ = 4.608V 0.75 INL ERROR (LSBs) C VOS ERROR (LSBs) 1 1.5 VDD = VAA+ = 5V VREF+ = 4.608V A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz C 0.5 B A 0.5 A 0.25 A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz 0 -60 0 B -60 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 6. INL vs TEMPERATURE FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE 1.0 VDD = VAA+ = 5V, VREF+ = 4.608V 0.75 DNL ERROR (LSBs) ERROR (LSBs) C 2 VDD = VAA+ = 5V, TA = 25oC CLK = 750kHz 1.5 0.5 B A FSE 1 DNL 0.5 INL VOS 0 0.25 A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz 0 -60 -40 -20 0 20 40 60 80 100 120 140 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 TEMPERATURE (oC) REFERENCE VOLTAGE, VREF (V) FIGURE 8. DNL vs TEMPERATURE FIGURE 9. ACCURACY vs REFERENCE VOLTAGE 2 VDD = VAA+ = 5V, VREF+ = 4.608V 1.5 FSE ERROR (LSBs) A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz C PSRR (LSBs) 0.5 VDD = VAA+ = 5V 5% CLK = 750kHz VREF+ = 4.0V 0.375 1 B 0.25 0.5 A 0.125 PSRR VOS PSRR FSE 0 -60 0 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (oC) TEMPERATURE (oC) FIGURE 10. FULL SCALE ERROR vs TEMPERATURE FIGURE 11. POWER SUPPLY REJECTION vs TEMPERATURE 6-1795 HI5812 Typical Performance Curves 8 VDD = VAA+ = 5V, VREF+ = 4.608V 7 SUPPLY CURRENT, IDD (mA) 6 5 4 3 2 1 0 -60 INTERNAL CLOCK AMPLITUDE (dB) (Continued) 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 -110.0 -120.0 -130.0 -140.0 0 500 INPUT FREQUENCY = 1kHz SAMPLING RATE = 50kHz SNR = 72.1dB SINAD = 71.4dB EFFECTIVE BITS = 11.5 THD = -79.1dBc PEAK NOISE = -80.9dB SFDR = -80.9dB -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (oC) 1000 FREQUENCY BINS 1500 2000 FIGURE 12. SUPPLY CURRENT vs TEMPERATURE FIGURE 13. FFT SPECTRUM 500 INTERNAL CLOCK FREQUENCY (kHz) VDD = VAA+ = 5V, VREF+ = 4.608V 450 12 11 400 ENOB (BITS) 350 300 250 200 150 -60 8 10 VDD = VAA+ = 5V 9 VREF+ = 4.608V TA = 25oC A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz C A B 7 -40 -20 0 20 40 60 80 100 120 140 0.1 1 10 100 TEMPERATURE (oC) INPUT FREQUENCY (kHz) FIGURE 14. INTERNAL CLOCK FREQUENCY vs TEMPERATURE FIGURE 15. EFFECTIVE BITS vs INPUT FREQUENCY -80 75 70 -70 SNR (dBc) THD (dBc) VDD = VAA+ = 5V VREF+ = 4.608V TA = 25oC -60 A. CLK =INTERNAL B. CLK = 750kHz C. CLK = 1MHz C -50 0.1 1 10 100 50 0.1 1 10 65 VDD = VAA+ = 5V VREF+ = 4.608V TA = 25oC A. CLK = INTERNAL B. CLK = 750kHz C. CLK = 1MHz A B C A B 60 55 100 INPUT FREQUENCY (kHz) INPUT FREQUENCY (kHz) FIGURE 16. TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY FIGURE 17. SIGNAL NOISE RATIO vs INPUT FREQUENCY 6-1796 HI5812 TABLE 1. PIN DESCRIPTIONS PIN NO. 1 NAME DRDY DESCRIPTION Output flag signifying new data is available. Goes high at end of clock period 15. Goes low when new conversion is started. Bit 0 (Least Significant Bit, LSB). Bit 1. Bit 2. Bit 3. Bit 4. Bit 5. Bit 6. Bit 7. Bit 8. Bit 9. Digital Ground (0V). Bit 10. Bit 11 (Most Significant Bit, MSB). Three-State Enable for D4-D11. Active low input. Analog Ground, (0V). Analog Positive Supply. (+5V) (See text.) Analog Input. Reference Voltage Positive Input, sets 4095 code end of input range. Reference Voltage Negative Input, sets 0 code end of input range. Start Conversion Input Active Low, recognized after end of clock period 15. CLK Input or Output. Conversion functions are synchronized to positive going edge. (See text.) Three-State Enable for D0 D3. Active Low Input. Digital Positive Supply (+5V). CLK IIN During the first three clock periods of a conversion cycle, the switchable end of every capacitor is connected to the input and the comparator is being auto-balanced at the capacitor common node. During the fourth period, all capacitors are disconnected from the input; the one representing the MSB (D11) is connected to the VREF+ terminal; and the remaining capacitors to VREF -. The capacitor-common node, after the charges balance out, will indicate whether the input was above 1/2 of (VREF+ - VREF -). At the end of the fourth period, the comparator output is stored and the MSB capacitor is either left connected to VREF+ (if the comparator was high) or returned to VREF -. This allows the next comparison to be at either 3/4 or 1/4 of (VREF+ - VREF -). At the end of periods 5 through 14, capacitors representing D10 through D1 are tested, the result stored, and each capacitor either left at VREF+ or at VREF -. At the end of the 15th period, when the LSB (D0) capacitor is tested, (D0) and all the previous results are shifted to the output registers and drivers. The capacitors are reconnected to the input, the comparator returns to the balance state, and the data-ready output goes active. The conversion cycle is now complete. Analog Input 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 VSS D10 D11 OEM VAAVAA+ VIN VREF+ VREFSTRT The analog input pin is a predominately capacitive load that changes between the track and hold periods of the conversion cycle. During hold, clock period 4 through 15, the input loading is leakage and stray capacitance, typically less than 5A and 20pF. At the start of input tracking, clock period 1, some charge is dumped back to the input pin. The input source must have low enough impedance to dissipate the current spike by the end of the tracking period as shown in Figure 18. The amount of charge is dependent on supply and input voltages. The average current is also proportional to clock frequency. 20 21 22 CLK 20mA 10mA 0mA 23 24 OEL VDD Theory of Operation HI5812 is a CMOS 12-Bit Analog-to-Digital Converter that uses capacitor-charge balancing to successively approximate the analog input. A binarily weighted capacitor network forms the A/D heart of the device. See the block diagram for the HI5812. The capacitor network has a common node which is connected to a comparator. The second terminal of each capacitor is individually switchable to the input, VREF+ or VREF -. 5V 0V 5V DRDY 0V 200ns/DIV. CONDITIONS: VDD = VAA+ = 5.0V, VREF+ = 4.608V, VIN = 4.608V, CLK = 750kHz, TA = 25oC FIGURE 18. TYPICAL ANALOG INPUT CURRENT 6-1797 HI5812 As long as these current spikes settle completely by end of the signal acquisition period, converter accuracy will be preserved. The analog input is tracked for 3 clock cycles. With an external clock of 750kHz the track period is 4s. A simplified analog input model is presented in Figure 19. During tracking, the A/D input (VIN) typically appears as a 380pF capacitor being charged through a 420 internal switch resistance. The time constant is 160ns. To charge this capacitor from an external "zero " source to 0.5 LSB (1/8192), the charging time must be at least 9 time constants or 1.4s. The maximum source impedance (RSOURCE Max) for a 4s acquisition time settling to within 0.5LSB is 750. If the clock frequency was slower, or the converter was not restarted immediately (causing a longer sample time), a higher source impedance could be tolerated. VIN RSW 420 CSAMPLE 380pF RSOURCE The HI5812 is specified with a 4.608V reference, however, it will operate with a reference down to 3V having a slight degradation in performance. A typical graph of accuracy vs reference voltage is presented. Full Scale and Offset Adjustment In many applications the accuracy of the HI5812 would be sufficient without any adjustments. In applications where accuracy is of utmost importance full scale and offset errors may be adjusted to zero. The VREF+ and VREF - pins reference the two ends of the analog input range and may be used for offset and full scale adjustments. In a typical system the VREF - might be returned to a clean ground, and the offset adjustment done on an input amplifier. VREF+ would then be adjusted to null out the full scale error. When this is not possible, the VREF input can be adjusted to null the offset error, however, VREF must be well decoupled. Full scale and offset error can also be adjusted to zero in the signal conditioning amplifier driving the analog input (VIN). Control Signal The HI5812 may be synchronized from an external source by using the STRT (Start Conversion) input to initiate conversion, or if STRT is tied low, may be allowed to free run. Each conversion cycle takes 15 clock periods. The input is tracked from clock period 1 through period 3, then disconnected as the successive approximation takes place. After the start of the next period 1 (specified by tD data), the output is updated. The DRDY (Data Ready) status output goes high (specified by tD1DRDY) after the start of clock period 1, and returns low (specified by tD2DRDY) after the start of clock period 2. The 12 data bits are available in parallel on three-state bus driver outputs. When low, the OEM input enables the most significant byte (D4 through D11) while the OEL input enables the four least significant bits (D0 - D3). tEN and tDIS specify the output enable and disable times. If the output data is to be latched externally, either the trailing edge of data ready or the next falling edge of the clock after data ready goes high can be used. When STRT input is used to initiate conversions, operation is slightly different depending on whether an internal or external clock is used. Figure 3 illustrates operation with an internal clock. If the STRT signal is removed (at least tRSTRT) before clock period 1, and is not reapplied during that period, the clock will shut off after entering period 2. The input will continue to track and the DRDY output will remain high during this time. A low signal applied to STRT (at least tWSTRT wide) can now initiate a new conversion. The STRT signal (after a delay of (tDSTRT)) causes the clock to restart. Depending on how long the clock was shut off, the low portion of clock period 2 may be longer than during the remaining cycles. - t AC Q R SOURCE(MAX) = ------------------------------------------------------------- - R SW -( N + 1 ) C SAMPLE In [ 2 ] FIGURE 19. ANALOG INPUT MODEL IN TRACK MODE Reference Input The reference input VREF+ should be driven from a low impedance source and be well decoupled. As shown in Figure 20, current spikes are generated on the reference pin during each bit test of the successive approximation part of the conversion cycle as the charge-balancing capacitors are switched between VREF - and VREF+ (clock periods 5 - 14). These current spikes must settle completely during each bit test of the conversion to not degrade the accuracy of the converter. Therefore VREF+ and VREF should be well bypassed. Reference input VREF - is normally connected directly to the analog ground plane. If VREF - is biased for nulling the converters offset it must be stable during the conversion cycle. 20mA IREF+ 10mA 0mA 5V CLK 0V DRDY 5V 0V 2s/DIV. CONDITIONS: VDD = VAA+ = 5.0V, VREF+ = 4.608V, VIN = 2.3V, CLK = 750kHz, TA = 25oC FIGURE 20. TYPICAL REFERENCE INPUT CURRENT 6-1798 HI5812 The input will continue to track until the end of period 3, the same as when free running. Figure 2 illustrates the same operation as above but with an external clock. If STRT is removed (at least tRSTRT) before clock period 2, a low signal applied to STRT will drop the DRDY flag as before, and with the first positive-going clock edge that meets the (tSUSTRT) setup time, the converter will continue with clock period 3. Clock The HI5812 can operate either from its internal clock or from one externally supplied. The CLK pin functions either as the clock output or input. All converter functions are synchronized with the rising edge of the clock signal. Figure 21 shows the configuration of the internal clock. The clock output drive is low power: if used as an output, it should not have more than 1 CMOS gate load applied, and stray wiring capacitance should be kept to a minimum. The internal clock will shut down if the A/D is not restarted after a conversion. The clock could also be shut down with an open collector driver applied to the CLK pin. This should only be done during the sample portion (the first three clock periods) of a conversion cycle, and might be useful for using the device as a digital sample and hold. If an external clock is supplied to the CLK pin, it must have sufficient drive to overcome the internal clock source. The external clock can be shut off, but again, only during the sample portion of a conversion cycle. At other times, it must be above the minium frequency shown in the specifications. In the above two cases, a further restriction applies in that the clock should not be shut off during the third sample period for more than 1ms. This might cause an internal charge-pump voltage to decay. If the internal or external clock was shut off during the conversion time (clock cycles 4 through 15) of the A/D, the output might be invalid due to balancing capacitor droop. An external clock must also meet the minimum tLOW and tHIGH times shown in the specifications. A violation may cause an internal miscount and invalidate the results. Except for VAA+, which is a substrate connection to VDD , all pins have protection diodes connected to VDD and VSS . Input transients above VDD or below VSS will get steered to the digital supplies. The VAA+ and VAA- terminals supply the charge-balancing comparator only. Because the comparator is autobalanced between conversions, it has good low-frequency supply rejection. It does not reject well at high frequencies however; VAA- should be returned to a clean analog ground and VAA+ should be RC decoupled from the digital supply as shown in Figure 22. There is approximately 50 of substrate impedance between VDD and VAA+. This can be used, for example, as part of a low-pass RC filter to attenuate switching supply noise. A 10F capacitor from VAA+ to ground would attenuate 30kHz noise by approximately 40dB. Note that back-to-back diodes should be placed from VDD to VAA+ to handle supply to capacitor turn-on or turn-off current spikes. Dynamic Performance Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the A/D. A low distortion sine wave is applied to the input of the A/D converter. The input is sampled by the A/D and its output stored in RAM. The data is than transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the converters dynamic performance such as SNR and THD. See typical performance characteristics. Signal-To-Noise Ratio The signal to noise ratio (SNR) is the measured RMS signal to RMS sum of noise at a specified input and sampling frequency. The noise is the RMS sum of all except the fundamental and the first five harmonic signals. The SNR is dependent on the number of quantization levels used in the converter. The theoretical SNR for an N-bit converter with no differential or integral linearity error is: SNR = (6.02N + 1.76) dB. For an ideal 12-bit converter the SNR is 74dB. Differential and integral linearity errors will degrade SNR. SNR = 10 Log Sinewave Signal Power Total Noise Power INTERNAL ENABLE CLK OPTIONAL EXTERNAL CLOCK CLOCK Signal-To-Noise + Distortion Ratio SINAD is the measured RMS signal to RMS sum of noise plus harmonic power and is expressed by the following: SINAD = 10 Log Sinewave Signal Power Noise + Harmonic Power (2nd - 6th) 100k 18pF FIGURE 21. INTERNAL CLOCK CIRCUITRY Effective Number of Bits The effective number of bits (ENOB) is derived from the SINAD data; ENOB = SINAD - 1.76 6.02 Power Supplies and Grounding VDD and VSS are the digital supply pins: they power all internal logic and the output drivers. Because the output drivers can cause fast current spikes in the VDD and VSS lines, VSS should have a low impedance path to digital ground and VDD should be well bypassed. 6-1799 HI5812 Total Harmonic Distortion The total harmonic distortion (THD) is the ratio of the RMS sum of the second through sixth harmonic components to the fundamental RMS signal for a specified input and sampling frequency. THD = 10 Log Total Harmonic Power (2nd - 6th Harmonic) Sinewave Signal Power Spurious-Free Dynamic Range The spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak. SFDR = 10 Log Sinewave Signal Power Highest Spurious Signal Power TABLE 2. CODE TABLE BINARY OUTPUT CODE INPUT VOLTAGE VREF+ = 4.608V VREF- = 0.0V (V) 4.6069 4.6058 3.4560 2.3040 1.1520 0.001125 0 MSB DECIMAL COUNT 4095 4094 3072 2048 1024 1 0 D11 1 1 1 1 0 0 0 D10 1 1 1 0 1 0 0 D9 1 1 0 0 0 0 0 D8 1 1 0 0 0 0 0 D7 1 1 0 0 0 0 0 D6 1 1 0 0 0 0 0 D5 1 1 0 0 0 0 0 D4 1 1 0 0 0 0 0 D3 1 1 0 0 0 0 0 D2 1 1 0 0 0 0 0 D1 1 1 0 0 0 0 0 LSB D0 1 0 0 0 0 1 0 CODE DESCRIPTION Full Scale (FS) FS - 1 LSB 3/ FS 4 1/ FS 2 1/ FS 4 1 LSB Zero The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage. +5V 0.1F 10F 0.1F 0.01F VAA+ VDD D11 . . . D0 DRDY OEM ANALOG INPUT VIN OEL STRT CLK VREFVAAVSS 4.7F VREF 4.7F 0.1F 0.001F OUTPUT DATA VREF+ 750kHz CLOCK FIGURE 22. GROUND AND SUPPLY DECOUPLING 6-1800 HI5812 Die Characteristics DIE DIMENSIONS: 3200m x 3940m METALLIZATION: Type: AlSi Thickness: 11kA 1kA PASSIVATION: Type: PSG Thickness: 13kA 2.5kA WORST CASE CURRENT DENSITY: 1.84 x 105 A/cm2 Metallization Mask Layout HI5812 D1 D0 (LSB) DRDY VDD OEL CLK D2 STRT D3 VREF - D4 D5 D6 VREF + D7 VIN D8 VAA + VAA - D9 VSS D10 D11 (MSB) OEM 6-1801 |
Price & Availability of HI5812
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |